
`include "shifter_defs.v"

`timescale 1ns / 1ps

// Attention : left is MSB and right is LSB

module shifterv2(
	i_left,
	i_right,
	i_data0,
	i_data1,
	i_sel,
	o_left,
	o_right,
	o_data
);

parameter DATA_WIDTH = 32;

input i_left;
input i_right;

input [DATA_WIDTH-1:0] i_data0; 
input [DATA_WIDTH-1:0] i_data1;
 
input [`SHIFTER_SEL_WIDTH-1:0] i_sel;

output o_left;
output o_right;

output [DATA_WIDTH-1:0] o_data;
reg [DATA_WIDTH-1:0] o_data;

always@( i_data0 or i_data1 or i_sel or i_left or i_right )
begin
	case( i_sel )
		`SHIFTER_SEL_ONE_LEFT	:		o_data = { i_left, i_data0[DATA_WIDTH-1:1] }; 		
		`SHIFTER_SEL_ONE_RIGHT:		o_data = { i_data0[DATA_WIDTH-2:0], i_right };
		`SHIFTER_SEL_NOP			:		o_data = i_data1;		
		default:									o_data = i_data0;		
	endcase
end

assign o_left  = i_data0[DATA_WIDTH-1]; 

assign o_right = i_data0[0];

endmodule
